Impact of parameter variation on the performance of LDMOS device compatible with SCI's 5V 180nm CMOS technology

Today, semiconductor industry derives about 10% of its multi-billion dollar revenue from power semiconductor devices. These are key components in any power management system. In recent years, the increased demand of System on Chip (SoC) applications has led to the integration of power devices and development of Smart Power ICs. Foundries have grown tremendously in terms of technology and semiconductor rocesses used for fabrication to accommodate for the contemporary needs. Device miniaturization has resulted in integration of billions of transistors on a single chip. Integration of high voltages devices has its own challenges. Handling high power on such minuscule dimensions has not been an easy task. In fact, we could not go below the 90nm node for power devices. Obtaining high breakdown voltage, low on-resistance and large SOA are major concerns along with reliability factors such as HCI and TDDB.



In the present work, a detailed analysis has been done on the performance of LDMOS devices compatible with SCL’s 5V 180nm CMOS technology. A design solution having both on and off state breakdown voltages scalable with drift length and having BV values ranging from 23V up to 45V has been proposed. Simulations have been done to avoid the undesirable Kirk effect, which often occurs due to the parasitic BJT present in LDMOS, and good I DSS acceptable limits. IDS-VDS characteristics have een obtained. On-resistance is within.