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  4. Bit-wise Logical Operations using Capacitor-less Silicon-on-Insulator MOSFET for In-memory Computing
 
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Bit-wise Logical Operations using Capacitor-less Silicon-on-Insulator MOSFET for In-memory Computing

Source
IEEE Electron Devices Technology and Manufacturing Conference Strengthening the Globalization in Semiconductors Edtm 2024
Date Issued
2024-01-01
Author(s)
Sharma, Prateek
Pal, Jaisingh
Lashkare, Sandip  
DOI
10.1109/EDTM58488.2024.10511766
Abstract
In this paper, Silicon-on-Insulator (SOI) MOSFET for capacitor-less in-memory computing (IMC) is proposed to demonstrate logical operations. A methodology is presented using 3 SOI MOSFETs to realize AND/OR logic operations using one of the SOI MOSFETs as a selector between AND/OR operations. The band-to-band tunneling physics-based charge storage in a sub-threshold regime allows energy-efficient data storage. The proposed capacitor-less architecture along with the high energy-efficiency has the potential to realize large-scale implementation of hardware IMC.
Unpaywall
URI
https://d8.irins.org/handle/IITG2025/29100
Subjects
Capacitor-less DRAM | Floating-body | In-memory Computing | SOI
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