Parasitic Capacitance in Nanosheet FETs: Extraction of Different Components and Their Analytical Modeling

This work presents an approach to extract and analytically model the components of the parasitic capacitance in the Nanosheet FETs. The model comprehensively accounts for parallel, fringing, and junction capacitance between the gate and the source/drain. The individual parasitic capacitance components are extracted from TCAD simulation by varying the structural and material parameters of the device, which are then used for model validation. The fringing parasitic capacitance components are modeled using the elliptical integral method based on the distribution of the electric field lines. The proposed model accurately incorporates the substantial (∼ 30%) contribution of junction capacitance to the total parasitic capacitance. The model uses only one fitting parameter and is accurate across the device structural variations with only ∼ 1.2% error.