Repository logo
  • English
  • العربية
  • বাংলা
  • Català
  • Čeština
  • Deutsch
  • Ελληνικά
  • Español
  • Suomi
  • Français
  • Gàidhlig
  • हिंदी
  • Magyar
  • Italiano
  • Қазақ
  • Latviešu
  • Nederlands
  • Polski
  • Português
  • Português do Brasil
  • Srpski (lat)
  • Српски
  • Svenska
  • Türkçe
  • Yкраї́нська
  • Tiếng Việt
Log In
New user? Click here to register.Have you forgotten your password?
  1. Home
  2. Scholalry Output
  3. Publications
  4. Structural and electrical characterization of phase evolution in epitaxial Gd2O3 due to anneal temperature for silicon on insulator application
 
  • Details

Structural and electrical characterization of phase evolution in epitaxial Gd2O3 due to anneal temperature for silicon on insulator application

Source
Thin Solid Films
ISSN
00406090
Date Issued
2024-11-15
Author(s)
Saurabh, Nishant
Patil, Shubham
Meihar, Paritosh
Kumar, Sandeep
Sharma, Anand
Kamaliya, Bhavesh Kumar
Mote, Rakesh G.
Lashkare, Sandip  
Laha, Apurba
Deshpande, Veeresh
Ganguly, Udayan
DOI
10.1016/j.tsf.2024.140559
Volume
808
Abstract
In this work, we understand the post-deposition anneal temperature effects on structural and electrical (leakage current and trap density) properties of epitaxial Gd<inf>2</inf>O<inf>3</inf> film grown on Si (111) substrate using a cost-effective and High-Volume Manufacturing capable radio frequency sputtering method. It is found that the Rapid Thermal Annealing (RTA) at an optimum temperature of 850 °C enhances the crystallinity of the cubic phase in film. However, at higher RTA temperatures (>900 °C to 1050 °C), Si out-diffusion in Gd<inf>2</inf>O<inf>3</inf> film is manifested as the reason for phase evolution towards the amorphous phase. The electrical characterization shows the film's low leakage current density of 100 nA/cm<sup>2</sup>. Moreover, increased breakdown voltage and field are observed with increasing RTA temperature. The frequency-dependent Capacitance-Voltage analysis shows a parallel shift accompanied by a kink at a lower frequency, indicating the presence of interface traps (D<inf>it</inf>) with a range of time constants. After the forming gas annealing, a significant reduction in D<inf>it</inf> is observed. The low leakage current density, low D<inf>it</inf> and high crystallinity make Gd<inf>2</inf>O<inf>3</inf> a promising candidate as a buried oxide in Silicon on Insulator MOSFETs.
Unpaywall
URI
https://d8.irins.org/handle/IITG2025/28659
Subjects
Capacitance-voltage | Epitaxial thin film | Gadolinium(III) oxide | Interface traps | Phase transformation | Silicon on insulator | Sputtering
IITGN Knowledge Repository Developed and Managed by Library

Built with DSpace-CRIS software - Extension maintained and optimized by 4Science

  • Privacy policy
  • End User Agreement
  • Send Feedback
Repository logo COAR Notify