Fast and Robust Sense Amplifier for Digital In Memory Computing

Digital In-Memory Computing (IMC) in SRAM promises a robust and energy-efficient solution to the Von Neumann bottleneck. This paper comprehensively analyzes the challenges associated with the technology scaling aspects of Sense Amplifier design for digital IMC. We show that the existing Sense Amplifier (SA) designs fail due to process variations at lower technology nodes resulting in incorrect compute outputs. Using our analysis, we show how the existing SA designs can be modified to obtain error-free output but with additional design constraints. We propose a novel area-efficient zero-error Compute-Enabled Sense Amplifier (CESA). We perform a detailed analysis of CESA, for which we have implemented 128 × 128 SRAM IMC array along with all the peripherals and compute logic in CMOS 28nm and show the CESA works correctly under process variations. The proposed CESA improves the compute access time and energy by 20.4% and 5.95%, respectively, and read access time and energy by 16.67% and 55.87%, respectively. The SRAM IMC with CESA and Compute circuit works at 1.43 GHz and has 56 TOPS/W/bit energy efficiency for the addition operation. Finally, we model the SA errors for neural networks and find that in LENET-5 NN, the accuracy degrades to ∼ 12% for SA with error, whereas the proposed error-free SA maintains the accuracy to its baseline value of 98.5%. Index Terms-SRAM, In Memory Computing, Sense Amplifier,