A 10T, 0.22fJ/Bit/Search Mixed-VTPseudo Precharge-Free Content Addressable Memory

Content Addressable Memories (CAMs) are high-speed hardware search engines that simultaneously perform a parallel search across the rows. This high speed comes at the cost of increased power. In CAMs, most of the power is consumed in the matchlines. Although precharge free CAMs eliminate the excessive power consumption due to the matchlines, they are comparatively slower than conventional CAMs. Further, our extensive Monte-Carlo (MC) simulation results show that existing precharge-free CAMs give false search results under process variations. In this brief, we propose a robust and energy-efficient pseudo-precharge-free CAM. For an array size of 32× 32 , the proposed design shows ∼ 221× energy-delay-product reductions compared to the existing precharge-free CAMs. In comparison with NOR-type CAM, the proposed design has ∼ 7.75× and ∼ 7.2× of energy-delay-product reduction for the array size of 32× 32 and 128 × 128 respectively. SPICE simulations were performed using Cadence Virtuoso in UMC 28nm technology node.