Modeling of Quantum Confinement and Capacitance in III-V Gate-All-Around 1-D Transistors

In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III-V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering the wave function penetration into the gate insulator, effective mass discontinuity at the semiconductor-oxide interface, 2-D confinement in the NW, and Fermi-Dirac statistics. The semiconductor charge expression proposed in this paper is completely explicit in terms of applied gate voltage, therefore, making it highly suitable for large circuit simulations. The model is also compared with the results from self-consistent Schrödinger-Poisson solver for different NW sizes and materials and found to be accurate over a wide range of gate voltages.