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  4. Computationally efficient analytic charge model for III-V cylindrical nanowire transistors
 
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Computationally efficient analytic charge model for III-V cylindrical nanowire transistors

Source
2018 Joint International Eurosoi Workshop and International Conference on Ultimate Integration on Silicon Eurosoi Ulis 2018
Date Issued
2018-05-03
Author(s)
Ganeriwala, Mohit D.
Marin, Enrique G.
Ruiz, Francisco G.
Mohapatra, Nihar R.  
DOI
10.1109/ULIS.2018.8354767
Volume
2018-January
Abstract
In this paper, we present a computationally efficient compact model for calculating the charges and gate capacitance of III-V cylindrical nanowire transistors. We proposed an approximation which decouples the Poisson and the Schrödinger equation and addresses the issues of developing a computationally efficient analytical model. Using the proposed approximation, we derived a model suitable for the circuit simulators. The model is physics based and does not include any empirical parameters. The accuracy of the model is verified across nanowires of different sizes and materials using simulation results from a 2D Poisson-Schrodinger solver.
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URI
https://d8.irins.org/handle/IITG2025/22863
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