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  4. A Compact Charge and Surface Potential Model for III-V Cylindrical Nanowire Transistors
 
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A Compact Charge and Surface Potential Model for III-V Cylindrical Nanowire Transistors

Source
IEEE Transactions on Electron Devices
ISSN
00189383
Date Issued
2019-01-01
Author(s)
Ganeriwala, Mohit D.
Ruiz, Francisco G.
Marin, Enrique G.
Mohapatra, Nihar R.  
DOI
10.1109/TED.2018.2866885
Volume
66
Issue
1
Abstract
Considering the demand of III-V multigate (MUG) transistors for next-generation CMOS technologies, a compact model is required to test their performance in different circuits. The low effective mass and highly confined geometry of these MUG devices demand the use of computationally expensive coupled Poisson-Schrödinger (PS) solver for terminal charges and surface potential. In this paper, we propose an approximation, which decouples the PS equations and enables the development of a computationally efficient analytical model. The surface potential and semiconductor charge equations for III-V low effective mass channel cylindrical nanowire (NW) transistors are derived using the proposed approximation. The proposed model is physics-based and does not include any empirical parameters. The accuracy of the model is verified across NWs of different sizes and materials using the data from the 2-D PS solver and found to be accurate.
Unpaywall
URI
https://d8.irins.org/handle/IITG2025/22683
Subjects
circuit simulation | compact modeling | III-V | MOS transistor | nanowire (NW) | quantum capacitance
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