Trap-assisted carrier transport through the multi-stack gate dielectrics of HKMG nMOS transistors: A compact model

In this paper, a compact model for the gate current in HKMG nMOS transistors is presented. The carrier transport through the multi-stack gate dielectrics of HKMG MOS transistors is shown to be dominated by the Trap Assisted Tunneling and Poole-Frenkel conduction mechanisms. Both these mechanisms occur simultaneously and each is dominant in a particular gate voltage range. The interdependence and simultaneity of both the mechanisms is modeled to get a compact gate current formulation. The model is valid for all gate voltages and for different temperatures. The model also includes the formulation of inelastic TAT in a compact format. The accuracy of the model is validated with the measurement data.