Guarded dual rail logic for soft error tolerant standard cell library

Electronic components have become an important part of space and military equipment. However, the environments in which these equipment are employed are very harsh as there are various kinds of radiations in space like heavy ions and lighter particles affecting circuits in different ways. Many different techniques to design radiation tolerant circuits have been proposed earlier and some of these techniques are discussed in this dissertation. A novel technique of designing an RHBD standard cell library termed as Guarded Dual-Rail Logic (GDRL) consist ing of complementary logic circuit and guard gates is proposed. The radiation immunity of GDRL has been proved through various simulations and it has been shown that on circuit level, the combinational cells are immune towards single event transients and sequential cells are immune towards single event upsets. It has also been proposed that with efficient layout design, the GDRL gates can be immune to single event multiple upsets. To further strengthen the claim of radi ation tolerance of the design, a test chip has been designed in 65 nm technology and is currently under fabrication. The chip is designed to run at 500 MHz. It con sists of benchmark circuits implemented with various radiation tolerant schemes prominent in the literature. The power requirements of GDRL design are 58% lesser than TMR but the area requirements are approximately thrice as compared with TMR. However, efficient layout design is expected to further reduce the area and power penalties in the GDRL design