Compact electrostatics and transport model for high mobility iii-v channel gate-all-around MOS transistors

Mohapatra, Nihar RanjanGaneriwala, Mohit D.Mohit D.Ganeriwala2025-09-042025-09-042020-01-01https://d8.irins.org/handle/IITG2025/32193ill.; 30 cm.13210026Electrical EngineeringSemiconductor MaterialsMOS TransistorsCircuit SimulatorsCross-sectional GeometriesCompact electrostatics and transport model for high mobility iii-v channel gate-all-around MOS transistorsPh.D.xxii, 123p.Ph.D.123456789/500