Sharma, PrateekPrateekSharmaPal, JaisinghJaisinghPalLashkare, SandipSandipLashkare2025-08-312025-08-312024-01-01[9798350371529]10.1109/EDTM58488.2024.105117662-s2.0-85193221359https://d8.irins.org/handle/IITG2025/29100In this paper, Silicon-on-Insulator (SOI) MOSFET for capacitor-less in-memory computing (IMC) is proposed to demonstrate logical operations. A methodology is presented using 3 SOI MOSFETs to realize AND/OR logic operations using one of the SOI MOSFETs as a selector between AND/OR operations. The band-to-band tunneling physics-based charge storage in a sub-threshold regime allows energy-efficient data storage. The proposed capacitor-less architecture along with the high energy-efficiency has the potential to realize large-scale implementation of hardware IMC.falseCapacitor-less DRAM | Floating-body | In-memory Computing | SOIConference Paper20240cpConference Proceeding0