N., Surana, NeelamSurana, NeelamN.M., Lavania, MiliLavania, MiliM.A., Barma, AbhishekBarma, AbhishekA.J., Mekie, JoyceeMekie, JoyceeJ.Di Natale, G.Bolchini, C.Vatajelu, E.-I.2025-09-012025-09-019.78E+1210.23919/DATE48585.2020.91163612-s2.0-85087413748https://www.scopus.com/inward/record.uri?eid=2-s2.0-85087413748&doi=10.23919%2FDATE48585.2020.9116361&partnerID=40&md5=942f36e6a10df5a5f6ea7d14b0588886https://d8.irins.org/handle/IITG2025/29375In this paper, we analyze the existing SRAM based In-Memory Computing(IMC) proposals and show through exhaustive simulations that they fail under process variations. 6-T SRAM, 8-T SRAM, and 10-T SRAM based IMC architectures suffer from compute-disturb (stored data flips during IMC), compute-failure (provides false computation results), and half-select failures, respectively. To circumvent these issues, we propose a novel 12-T Dual Port Dual Interlockedstorage Cell (DPDICE) SRAM. DPDICE SRAM based IMC architecture(DPDICE-IMC) can perform essential boolean functions successfully in a single cycle and can perform basic arithmetic operations such as add and multiply. The most striking feature is that DPDICE-IMC architecture can perform IMC on two datasets simultaneously, thus doubling the throughput. Cumulatively, the proposed DPDICE-IMC is 26.7%, 8�, and 28% better than 6-T SRAM, 8-T SRAM, and 10-T SRAM based IMC architectures, respectively. � 2020 Elsevier B.V., All rights reserved.EnglishMemory architectureArithmetic operationsDual portExhaustive simulationProcess VariationShow throughSingle cycleStatic random access storageConference paper2020911636112