Kaur, RaminderRaminderKaurSurana, NeelamNeelamSuranaMekie, JoyceeJoyceeMekie2025-08-302025-08-302017-10-31[9781509043668]10.1109/RADECS.2016.80931442-s2.0-85043583654https://d8.irins.org/handle/IITG2025/23007A novel technique that combines complementary dual rail logic and guard gate, referred to as Guarded Dual Rail Logic (GDRL) to mitigate single event effects is proposed in this paper. TCAD simulations have been done to validate the SET filtering properties of guard gate in 65nm technology for LET values up to 100MeV-cm²/mg. To compare proposed GDRL design with TMR, we have used ISCAS benchmark circuits. Circuits designed with proposed technique consume ∼57% less power compared to their TMR implementation.falsecharge sharing | dual rail logic | single event transients | single event upsets | standard cell libraryConference Paper1-431 October 20175cpConference Proceeding6