Controlling the Clamping Voltage in Punch-Through Diodes via N+ Well and Contact Design for Low Voltage System Level ESD Protection

Likhitkar, PrafulPrafulLikhitkarMaheshwari, NavinNavinMaheshwariLashkare, SandipSandipLashkare2025-08-312025-08-312025-01-01[9798331504168]10.1109/EDTM61175.2025.110407502-s2.0-105010820138https://d8.irins.org/handle/IITG2025/28337A low voltage Electrostatic Discharge protection device is essential for low-voltage interfaces such as low-voltage MDIOs, Next-gen USB, and Thunderbolt interfaces. Here, a four-layer (n++p+p-n+) punch through diode is studied comprehensively, emphasizing lowering clamping voltage (Vclamp) by reducing dynamic resistance (RDYN). Further, two advanced designs with multi-contact & n+ well design are proposed to reduce the RDYN. The n+ well design lowers the RDYN by ~ 30%, lowering the Vclamp and enhancing IC protection.falseClamping Voltage | Dynamic ResistanceControlling the Clamping Voltage in Punch-Through Diodes via N+ Well and Contact Design for Low Voltage System Level ESD ProtectionConference Paper20250cpConference Proceeding0