Mohapatra, Nihar RanjanViswakarma, Manish KumarManish KumarViswakarma2025-09-042025-09-042016-01-01https://d8.irins.org/handle/IITG2025/32121ABSTRACT Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant Digital Circuit. SAR ADC for this work does not require an op-amp, so they are advantageous in CMOS technology scaling. The architecture is often the best choice for battery-powered bio-medical devices or mobile applications which need medium resolution (8-14 bits), medium speed (1K/s - 100 MS/s) and require low-power consumption. This work is more focus on how we can design Low Power SAR ADC so that the battery life is increased for bio-medical devices. The work researches, to minimize the power consumption of DAC circuit by splitting the DAC Circuit into 3 sub DAC. By splitting the total DAC into 3 sub DAC (4, 4 and 6) the maximum value of capacitance is reduced by a factor of 256 in comparison with conventional DAC. In this work the 14-bit low power differential SAR ADC is implemented in UMC 180 nm which consumes 4.63_W.col.; ill.; 30 cm.CMOS Technology ScalingLow-Power ConsumptionDAC CircuitUMC 180 nmAnalog To Digital ConvertersM.Tech57p.M.Tech123456789/500