Glint, TomTomGlintPrasad, KailashKailashPrasadDagli, JinayJinayDagliGandhi, KrishilKrishilGandhiGupta, AryanAryanGuptaPatel, VrajeshVrajeshPatelShah, NeelNeelShahMekie, JoyceeJoyceeMekie2025-08-312025-08-312023-01-16[9781450397834]10.1145/3566097.35678662-s2.0-85148485304https://d8.irins.org/handle/IITG2025/26920Emerging data intensive AI/ML workloads encounter memory and power wall when run on general-purpose compute cores. This has led to the development of a myriad of techniques to deal with such workloads, among which DNN accelerator architectures have found a prominent place. In this work, we propose a hardware-software co-design approach to achieve system-level benefits. We propose a quantized data-aware POSIT number representation that leads to a highly optimized DNN accelerator. We demonstrate this work on SOTA SIMBA architecture, extendable to any other accelerator. Our proposal reduces the buffer/storage requirements within the architecture and reduces the data transfer cost between the main memory and the DNN accelerator. We have investigated the impact of using integer, IEEE floating point, and posit multipliers for LeNet, ResNet and VGG NNs trained and tested on MNIST, CIFAR10 and ImageNet datasets, respectively. Our system-level analysis shows that the proposed approximate-fixed-posit multiplier when implemented on SIMBA architecture, achieves on average ∼2.2× speed up, consumes ∼3.1× less energy and requires ∼3.2× less area, respectively, against the baseline SOTA architecture, without loss of accuracy (∼±1%).falseco-design | DNN accelerators | neural networksConference Paper469-47416 January 20235cpConference Proceeding2