Ved, Sneha N.Sneha N.VedSingh, SarabjeetSarabjeetSinghMekie, JoyceeJoyceeMekie2025-08-312025-08-312019-01-0110.1145/32410512-s2.0-85061101466https://d8.irins.org/handle/IITG2025/23403Communication between different IP cores in MPSoCs and HMPs often results in clock domain crossing. Asynchronous network on chip (NoC) support communication in such heterogeneous set-ups. While there are a large number of tools to model NoCs for synchronous systems, there is very limited tool support to model communication for multi-clock domain NoCs and analyse them. In this article, we propose the Pluggable Asynchronous NEtwork on Chip (PANE) simulator, which allows system-level simulation of asynchronous network on chip (NoC). PANE allows design space exploration of synchronous, asynchronous, and mixed synchronous-asynchronous(heterogeneous) NoC for various system-level NoC parameters such as packet latencies, throughput, network saturation point and power analysis. PANE supports a large range of NoC configurations-routing algorithms, topologies, network sizes, and so on-for both synthetic and real traffic patterns. We demonstrate the application of PANE by using synchronous routers, asynchronous routers, and a mix of asynchronous and synchronous routers. One of the key advantages of PANE is that it allows a seamless transition from synchronous to asynchronous NoC simulators while keeping pace with the developments in synchronous NoC tools as they can be integrated with PANE.falseAsynchronous simulator | Heterogeneous systems | NoCArticle15504840January 201947arJournal3WOS:000459794400007