Kaushal, Kumari NeerajKumari NeerajKaushalMohapatra, Nihar R.Nihar R.Mohapatra2025-08-312025-08-312021-01-0110.1109/JEDS.2021.30598542-s2.0-85100945629https://d8.irins.org/handle/IITG2025/25559In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication and measurement on different test structures, we have shown that the graded channel significantly improves the drive capability (upto 30%), analog FoMs and hot-carrier reliability of LDMOS transistors without any penalty on the OFF-state performance. The performance improvement is independent of drift region design (breakdown voltage). The device physics behind different observations is also discussed with detailed TCAD simulations.truebreakdown voltage | doping gradient | electron velocity | hot carrier reliability | LDMOS | output conductance | PMIC | specific on-resistance | trans-conductanceArticlehttps://ieeexplore.ieee.org/ielx7/6245494/9359727/09355405.pdf21686734334-3412021139355405arJournal12