Bhoir, Mandar S.Mandar S.BhoirKaushal, Kumari NeerajKumari NeerajKaushalPanda, Soumya R.Soumya R.PandaSingh, Amit K.Amit K.SinghJatana, H. S.H. S.JatanaMohapatra, Nihar R.Nihar R.Mohapatra2025-08-312025-08-312019-11-0110.1109/TED.2019.29423722-s2.0-85074454777https://d8.irins.org/handle/IITG2025/23150In this article, we have proposed a simple, novel, and cost-effective technique to mitigate the ON-state performance issues in laterally diffused MOS (LDMOS) transistors. We propose a novel technique-LDMOS transistor with source-side underlap (SU), which can be integrated into any existing LDMOS/bipolar-CMOS-DMOS (BCD) process flow without any additional processing/area cost. Unlike commonly used solutions, the SU LDMOS provides flexibility to improve ON-state behavior without disturbing other performance metrics. The proposed SU LDMOS transistor is experimentally demonstrated using 180-nm CMOS technology, and noteworthy improvement in ON-state breakdown voltage, electrical safe operating area (SOA), output conductance, transistor intrinsic gain, and cutoff frequency is reported. The physics behind the improvement is also discussed in detail.falseAnalog/radio frequency (RF) performance | breakdown-voltage | laterally diffused MOS (LDMOS) | output conductance | safe operating area (SOA) | source-side underlap (SU) | trans-conductanceArticle155796464823-4828November 2019138856264arJournal14