Mekie, JoyceeJoyceeMekie2025-08-302025-08-302014-01-01[9781479937899]10.1109/ASYNC.2014.132-s2.0-84903828303https://d8.irins.org/handle/IITG2025/21283In this paper we analyze the effect of dynamic frequency scaling on the complexity of interface design in rationally-related multi-clocked systems. Static timing analysis of rationally-related modules can be used to design robust, error-free interfaces as shown in previous work. In systems with dynamic frequency scaling, however, timing analysis needs to be carried out for each possible frequency. We present a partially automated tool that aids in performing timing analysis and allows interface design to be optimized. We demonstrate the feasibility of our approach and the benefits of tool support in optimizing interface design through a case-study. The interface circuit has been simulated using both SPICE and Verilog. © 2014 IEEE.falseAutomated analysis | Dynamic frequency scaling | Rational clocks | SynchronizationConference Paper2643148337-44201406835809cpConference Proceeding0