Sivanaresh, M. SatyaM. SatyaSivanareshMohapatra, Nihar RanjanNihar RanjanMohapatra2025-08-302025-08-302015-04-0110.1109/TED.2015.23988702-s2.0-84926020337https://d8.irins.org/handle/IITG2025/22033This paper analyzes and models the narrow width effect (NWE) observed in nMOS transistors fabricated using a 28-nm gate-first CMOS process. It is shown that the threshold voltage of nMOS transistors increases with decrease in channel width and this effect is enhanced at shorter gate lengths, thicker hafnium oxide (HfO<inf>2</inf>), and thicker lanthanum (La) capping layer. It is also observed that this increase in threshold voltage for narrow width transistors is influenced by the device layout. The physical mechanisms responsible for the observed anomalous behavior are identified through measurements on different test structures. An empirical model is proposed to understand and model this behavior. The accuracy of the model is verified by comparing it with the experimental data. It is finally proposed that the observed NWE could be minimized by optimizing the thickness of HfO<inf>2</inf>, La capping layer, and SiO<inf>2</inf> interfacial layer and by using different device layouts.falseDevice scaling | effective work function (EWF) | high-K dielectric | high-K dielectrics and metal gate (HKMG) | lanthanum (La)-induced dipoles | layout-dependent effects | metal gate | MOS transistor | narrow width effect (NWE) | oxygen vacancies | threshold voltage | transconductance enhancementArticle1085-10911 April 201577046381arJournal7WOS:000351753900002