Effects of small geometries on the performance of gate first high- κ metal gate NMOS transistors

Walke, Amey M.Amey M.WalkeMohapatra, Nihar R.Nihar R.Mohapatra2025-08-302025-08-302012-08-2110.1109/TED.2012.22086472-s2.0-84866728834https://d8.irins.org/handle/IITG2025/21039This paper discusses in detail the effect of small geometries on the performance of NMOS transistors fabricated using a 28-nm gate-first CMOS technology. It is shown that the threshold voltage and transconductance of the NMOS transistors increase with the decrease in the channel width, and this effect is enhanced at shorter gate lengths. PMOS transistors show conventional width dependence. The possible physical mechanisms responsible for this anomalous behavior are identified and explained through detailed measurements. A 2-D charge-distribution-based model is proposed to model this anomalous effect. The accuracy of the proposed model is verified by comparing it with the experimental and simulated data. © 2012 IEEE.falseDevice scaling | high-κ dielectric | La-induced dipoles | metal gate | narrow-width effects (NWEs) | transconductance enhancementEffects of small geometries on the performance of gate first high- κ metal gate NMOS transistorsArticle2582-2588201256269076arJournal6