Surana, NeelamNeelamSuranaMekie, JoyceeJoyceeMekieMohapatra, Nihar RanjanNihar RanjanMohapatra2025-08-302025-08-302017-12-01[9781538629079]10.1109/EDSSC.2017.81265742-s2.0-85043452948https://d8.irins.org/handle/IITG2025/22998This paper shows the circuit level performance comparison of low-κ and high-κ spacer Junctionless FinFET(J-FinFET). TCAD simulations show that for high-κ (HfO<inf>2</inf>, κ=22) spacer J-FinFET, the device performance parameters such as DIBL (drain induced barrier lowering), SS (sub-threshold swing) and ION/IOFF improved by 14.5 % , 5% and 3.5x respectively as compared to low-κ (SiO2, κ=3.9) spacer J-FinFET. Interestingly, the same is not true for the circuitlevel parameters. Results of circuit-level performances show that for high-κ spacer J-FinFET circuits, delay and power consumption is increased by minimum 40% and 36%, respectively, as compared to their corresponding low-κ spacer J-FinFET circuits. Our analysis shows that performance degradation in high-κ spacer J-FinFET is due to increased fringe capacitance in high-κ spacer J-FinFET.falseCircuit performance | J-FinFET | SpacerConference Paper1-21 December 20172cpConference Proceeding2