Bhoir, Mandar S.Mandar S.BhoirChiarella, ThomasThomasChiarellaRagnarsson, Lars AkeLars AkeRagnarssonMitard, JeromeJeromeMitardTerzeiva, ValentinaValentinaTerzeivaHoriguchi, NaotoNaotoHoriguchiMohapatra, Nihar R.Nihar R.Mohapatra2025-08-312025-08-312019-01-0110.1109/JEDS.2019.29345752-s2.0-85076520121https://d8.irins.org/handle/IITG2025/23405This paper discusses in detail the effects of Sub-10nm fin-width ( W<inf>fin</inf> ) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the trans-conductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm W<inf>fin</inf> regime, cannot be improved just by W<inf>fin</inf> scaling but by optimizing source/drain resistance, gate dielectric thickness together with the W<inf>fin</inf> scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.trueanalog/RF | FinFET | mobility | output conductance | series resistance | sub-10nm fin-width | technology scaling | transconductance | variabilityArticlehttps://ieeexplore.ieee.org/ielx7/6245494/8656606/08794627.pdf216867341217-1224201998794627arJournal9