An Indigenous Low-Cost Robust BiCMOS Process Flow for NavIC Applications

Maheshwari, OmOmMaheshwariKatiyar, RavinsRavinsKatiyarDasgupta, AmitavaAmitavaDasguptaChakravorty, AnjanAnjanChakravortyNair, Deleep R.Deleep R.NairMohapatra, Nihar R.Nihar R.Mohapatra2025-08-312025-08-312022-01-01[9781665491853]10.1109/ICEE56203.2022.101183182-s2.0-85160529100https://d8.irins.org/handle/IITG2025/27132A low-cost BiCMOS process integrable with Semi-Conductor Laboratory's (SCL's) 180 nm CMOS process flow is developed for designing indigenous application-specific integrated circuits (ASICs) for Indian regional satellite navigation system NavIC. The process is optimized for realizing high frequency (HF) as well as high voltage (HV) double polysilicon bipolar junction transistors and is robust to process variations. The designed HF device has fT/fmax 29/50 GHz, and the HV device has a breakdown voltage of 10 V.falseBiCMOS Process | Double Polysilicon BJT | IRNSS | Low-Cost | NavIC | RobustAn Indigenous Low-Cost Robust BiCMOS Process Flow for NavIC ApplicationsConference Paper20220cpConference Proceeding0