Mohapatra, SatyajitSatyajitMohapatraMohapatra, Nihar RanjanNihar RanjanMohapatra2025-08-312025-08-312020-01-01[9781728157016]10.1109/VLSID49098.2020.000302-s2.0-85089174567https://d8.irins.org/handle/IITG2025/24307The frontend Analog to Digital Converters (ADCs) consume substantial power in implanted biomedical devices such as cardiac defibrillators. Their energy efficiency primarily determines the lifetime of these miniaturized micro powered devices. In this work, the design and calibration of a 14-bit 10 KS/s SAR ADC using SCL 0.18\mu m2P4M CMOS processes is discussed. The designed ADC occupies a layout area of 2.4mm\times2.4mm and consumes \sim19\muw at 10 KS/s speed. It achieves an effective resolution (ENOB) of 13.84 bits with an energy Figure of merit (FOM) of 139 fJ/conversion. The design is verified at all process corners over the commercial temperature range (0-85{\circ}\mathrm{C}).falseAnalog to Digital conversion | Capacitor Mismatch | Digital Calibrations | Energy Efficiency | Placement optimizationConference Paper72-77January 202059105443cpConference Proceeding2