Effect of channel dimensions and spacer material on drain saturation voltage (VDS,SAT ) of sub-10nm Wf in regime FinFETs

Mohapatra, Nihar RanjanSharma, PratikPratikSharma2025-09-042025-09-042021-01-01https://d8.irins.org/handle/IITG2025/32280ill.; hbk.; 30 cm.19210091Electrical EngineeringElectron DevicesMOS TransistorSolid-State ElectronicsMicroelectronicsVLSI SystemsEffect of channel dimensions and spacer material on drain saturation voltage (VDS,SAT ) of sub-10nm Wf in regime FinFETsM.Techviii, 61p.M.Tech123456789/500