Mekkattillam, YadukrishnanYadukrishnanMekkattillamMohapatra, SatyajitSatyajitMohapatraMohapatra, Nihar R.Nihar R.Mohapatra2025-08-312025-08-312019-01-01[9789813297661]10.1007/978-981-32-9767-8_492-s2.0-85077133374https://d8.irins.org/handle/IITG2025/24387This work presents the design and calibration of an ultra-low power 14-bit 10 KS/s fully differential split SAR ADC. The integrated transient response of the ADC shows a settling accuracy of 32 µ V within 50 µ s while consuming only 19.5 µ W power. The simulated post-layout spectrum yields an SNDR of 84.5 dB with an effective linearity of 13.8 bits. The ADC occupies a total area of 2.5 mm x 2.5 mm when implemented in the SCL 0.18 µ m 2P4M CMOS processes. The implementation is shown to be highly power efficient with an energy figure of merit of 140 fJ/conversion step. The challenges faced during the full chip implementation of the ADC and techniques used to overcome them at various levels of design hierarchy are discussed in details.falseCapacitor mismatch | Differential SAR | Digital correction | Placement optimization | Redundancy | Tri-level switchingConference Paper18650937590-60420195cpBook Series5