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  4. From Variations to Precision: Modeling and Optimization of Inner Spacer Etch in GAA FETs
 
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From Variations to Precision: Modeling and Optimization of Inner Spacer Etch in GAA FETs

Source
Asmc Advanced Semiconductor Manufacturing Conference Proceedings
ISSN
10788743
Date Issued
2025-01-01
Author(s)
Maheshwari, Om
Kumar, Pardeep
Barai, Samit
Mohapatra, Nihar R.  
DOI
10.1109/ASMC64512.2025.11010557
Abstract
This work introduces a robust machine learning framework for modeling and optimizing the inner spacer etch process in gate-all-around FET fabrication. Using an in-house Particle Monte-Carlo simulator, the etch process is modeled precisely across varied conditions. Gaussian Process Regression outperforms neural network models, achieving 98-99% accuracy in predicting etch front variations. Bayesian Optimization with adaptive sampling and successive domain reduction is utilized to fine-tune etch parameters, minimizing the error between predicted and target etch fronts. This integrated approach enables precise control over spacer-channel geometry, making this approach highly effective for advanced semiconductor manufacturing.
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URI
https://d8.irins.org/handle/IITG2025/28373
Subjects
Bayesian optimization | gate all around FETs | Gaussian Process Regression | inner spacer etching | nanoPMC | Particle Monte-Carlo
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