Novel Design of a Silicon Photodetector and its Integration in a 4x4 CMOS Pixel Array

High performance pixel design for 550Ke full well capacity, 101 mu m pixel pitch and 65dB dynamic range is challenging on typical CMOS process. In general silicon processes are un-optimized for critical optical parameters. Therefore, the spectral response and photo-sensitive simulation are the immediate requirements. This paper highlights a methodology for high performance imaging pixel design in a typical CMOS process and optimizing its quantum efficiency over a wide spectral range of 0.1 mu to 0.9 mu m wavelength. It also introduces an design approach for such systems with the help of TCAD tool for photo sensitivity simulation and HSPICE simulator for integrated performance verification. The quantum efficiency of pixels has been optimized through layout design technique and verified through TCAD simulation. The integrated simulation shows good agreement with post-layout simulation of a test chip design of 4X4 pixel area array for 50% quantum efficiency and dynamic range of more than 65dB using 180 nm CMOS process.