Development of Low-Cost Silicon BJT Technology and Modeling

BiCMOS technology enables VLSI circuits with high current driving capability and optimized speed-power-density performance when compared to standalone bipolar or CMOS technologies. In this work, we present the device design, process development and optimization of diffusion poly-emitter bipolar junction transistor (BJT), for the first time in India, for analog and RF applications. The baseline 180 nm CMOS process of Semi-Conductor Lab at Chandigarh (India) is used to develop the BiCMOS process. All the TCAD simulations are calibrated with the measured data of baseline BJT from 180 nm CMOS process. Calibrated simulations of our proposed poly-emitter BJT show current gain > 140 and current driving capacity > 10 mA. The breakdown voltage of the transistor is above 5 V ($\text{BV}_{CEO}$) with cut-off frequency ($f_{T}$) and maximum oscillation frequency ($f_{max}$) more than 17 GHz and 40 GHz, respectively.