Guarded dual rail logic for soft error tolerant standard cell library

A novel technique that combines complementary dual rail logic and guard gate, referred to as Guarded Dual Rail Logic (GDRL) to mitigate single event effects is proposed in this paper. TCAD simulations have been done to validate the SET filtering properties of guard gate in 65nm technology for LET values up to 100MeV-cm²/mg. To compare proposed GDRL design with TMR, we have used ISCAS benchmark circuits. Circuits designed with proposed technique consume ∼57% less power compared to their TMR implementation.