Soft error tolerant designs using guarded dual rail logic

Circuits that need to operate in harsh environments such as in space, military, nuclear reactors, etc. need to be designed carefully as they are subjected to ex- ternal irradiations. In this context, Radiation Hardening By Design(RHBD) has gained much importance in the last couple of decades. Radiations can lead to temporary or permanent failures in the designs. While hard-errors, which cause physical damage to ICs are hard to deal with, plenty of approaches have been proposed to deal with soft-errors. In this thesis, we explore novel techniques to safe-guard against soft-errors that occur in combinational and sequential logic. The soft errors include, single event transiets (SET), single event upset (SEU) and multiple event transient (MET). A novel technique to deal with SETs in combinational circuit called Guarded Dual-Rail Logic (GDRL) was proposed in [28]. GDRL combines complementary dual rail logic and a guard gate to lter out the SETs. In this thesis we have extended this work to implement system-level, large and complex digital designs using GDRL. We have compared GDRL against the well known Triple Modular Redundancy (TMR) and Gate sizing (GS) techniques for radiation hardening. The International Symposium on Circuits and Systems (ISCAS) `85 benchmark circuits suite has been used for comparison. We have developed a completely automated CAD tool ow for circuit synthesis for GDRL, TMR, GS designs. Our results show that benchmark circuits implemented using GDRL consumes about 20-60% less power as compared to TMR and about 40??60% in comparison to GS. The area occupied by GDRL is comparable with TMR and GS. However, we nd that GDRL is approximately two times slower than TMR. Partial GDRL, has been proposed an alternative to GDRL to overcome the delay penalty. In partial GDRL, only the logic gates providing the nal outputs are hardened for radiation. While this technique consumes around 50% less area and power compared to the TMR but is far susceptible to radiations as compare to both TMR and full GDRL. Apart from SETs in combinational circuits, we have also studied SEUs in sequential designs. We have compared the sequential pipelines designed using radiation hardened DICE, FERST, TMR and TAG-4 latches proposed in earlier works with GDRL logic in combinational circuit. We show that a complete radiation hardened sequential pipeline design can be ob- tained by by combining full GDRL combinational logic with TAG-4 latches. We have studied the e ectiveness of GDRL for dealing with METs and compared it against TMR for several combinational gates. We nd that GDRL is about 1.5-2 times more error-tolerant than TMR for METs. Finally, we have implemented ve di erent benchmarks on an ASIC to be fabricated in SCL 180nm technology node. We have taped out a complete with four di erent benchmarks and tested it for logical correctness. The radiation test on this fabricated IC carried will be carried out in future.