A mismatch resilient 16-bit 20 MS/s pipelined ADC

In various imaging applications with relaxed Integrated Non-Linearity (INL) requirements, the Commutated Feedback Capacitor Switching (CFCS) technique enables scaling down the sampling capacitors to the thermal limits. The 3.5-bit MDAC architecture combined with CFCS has been envisaged to provide high linearity with power requirement needed for high resolution space imaging applications. In this work, we have discussed various design challenges involved in the design and implementation of the 3.5-bit MDAC with MCS-CFCS architecture. We have proposed various techniques that helps to overcome the linearity constraints at the sub-module, module and chip level. We have designed a 5mm×5mm prototype ADC which consumes 240mW of power (when designed using 1P6M UMC 0.18?m CMOS process). Our design achieves an ENOB of 15.4 bits and FoM of 289 fJ/conversion step. Various design challenges faced during the implementation of the ADC and techniques to overcome them are discussed in details.