Repository logo
  • English
  • العربية
  • বাংলা
  • Català
  • Čeština
  • Deutsch
  • Ελληνικά
  • Español
  • Suomi
  • Français
  • Gàidhlig
  • हिंदी
  • Magyar
  • Italiano
  • Қазақ
  • Latviešu
  • Nederlands
  • Polski
  • Português
  • Português do Brasil
  • Srpski (lat)
  • Српски
  • Svenska
  • Türkçe
  • Yкраї́нська
  • Tiếng Việt
Log In
New user? Click here to register.Have you forgotten your password?
  1. Home
  2. Scholalry Output
  3. Publications
  4. Rapid Tracking of Grid Variables Using Prefiltered Synchronous Reference Frame PLL
 
  • Details

Rapid Tracking of Grid Variables Using Prefiltered Synchronous Reference Frame PLL

Source
IEEE Transactions on Instrumentation and Measurement
ISSN
00189456
Date Issued
2015-07-01
Author(s)
Subramanian, Chandrasekaran
Kanagaraj, Ragavan  
DOI
10.1109/TIM.2014.2366275
Volume
64
Issue
7
Abstract
For synchronization applications, synchronous reference frame (SRF) phase-locked loop (PLL) is widely deployed. Its performance is excellent when the input voltage consists of only fundamental positive sequence (FPS) component. If the grid voltage is unbalanced or polluted with harmonics and dc offset, its performance degrades. Many modifications were proposed to address this issue. However, the removal of dc offset and fundamental negative sequence (FNS) component without compromising the dynamic performance still remains a challenging task. To this end, this paper presents a rapid Type-1 SRF PLL scheme with preloop filtering stage for tracking the attributes of grid voltage FPS component. Fixed sampling period sliding discrete Fourier transform (SDFT) and instantaneous symmetrical components method are employed in the preloop stage. With this modification, the dc offset, harmonics and the FNS component are rejected and only the FPS component enters the PLL. As a result, transients vanish quickly. However, when the grid frequency drifts, SDFT causes amplitude and phase errors, and Type-1 PLL introduces a steady-state tracking error in phase. These errors are compensated with the help of an error correction criteria. Robustness and the improved transient response of the proposed scheme are demonstrated with an experimental study involving real-time controller board (dSPACE DS1104) and three-phase programmable power source.
Unpaywall
URI
https://d8.irins.org/handle/IITG2025/22641
Subjects
Frequency estimation | grid synchronization | phase estimation | phase-locked loop (PLL) | sliding discrete Fourier transform (SDFT)
IITGN Knowledge Repository Developed and Managed by Library

Built with DSpace-CRIS software - Extension maintained and optimized by 4Science

  • Privacy policy
  • End User Agreement
  • Send Feedback
Repository logo COAR Notify