On the improved RF performance of step field plate LDMOS transistor

This paper presents an analysis of the Step Field Plate Laterally Diffused Metal Oxide Semiconductor (SFP LDMOS) structure for improved high power and RF performance. The proposed structure is cost-effective, CMOS integrable, and has a high power figure of merit (FoM) due to its high off-state breakdown voltage (BV<inf>DS,off</inf>) and low specific on-resistance (R<inf>sp</inf>). Significant improvement in frequency behavior is observed, as demonstrated by the flatter trans-conductance (g<inf>m</inf>), 12.5x lower gate-to-drain capacitance (C<inf>gd</inf>), 2.5x lower gate-to-source capacitance (C<inf>gs</inf>), and lower output conductance (g<inf>ds</inf>). Single tone and double tone analyses are performed on an RF PA circuit implemented in TCAD. Results show ∼5 dBm higher output power (P<inf>out</inf>), ∼6 dB higher power gain, and 46% higher drain efficiency (η), which are attributed to ∼1.9x lower drain-to-source capacitance (C<inf>ds</inf>) and ∼15 dBm lower magnitude of third-order intermodulation distortion due to lower third order derivative of drain current (I<inf>D</inf>). The paper also explains the device physics behind these observations.