A computationally efficient compact model for trap-assisted carrier transport through multi-stack gate dielectrics of HKMG nMOS transistors

This paper analyzes in detail the carrier transport through the multi-stack gate dielectrics of high-K metal gate (HKMG) nMOS transistors under different gate biases and temperatures. The existing uncertainty about the carrier transport mechanisms for different gate biases is resolved through accurate band diagram analysis and gate current measurement under different conditions. The trap assisted tunneling (elastic and inelastic) and Poole-Frenkel conduction are identified as the two dominant mechanisms of carrier transport. These two mechanisms are found to be prevalent in different gate bias ranges and have distinct signatures. A computationally efficient compact model for the gate current in HKMG nMOS transistors is developed capturing the simultaneity of both the carrier transport mechanisms. The proposed model is valid for all gate voltages (accumulation to inversion) and for different temperatures. The accuracy of the proposed model is confirmed by comparing it with the experimental data.