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  4. Performance optimized 64b/66b line encoding technique for high speed SERDES devices
 
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Performance optimized 64b/66b line encoding technique for high speed SERDES devices

Source
Communications in Computer and Information Science
ISSN
18650929
Date Issued
2017-01-01
Author(s)
Singh, Jatindeep
Mohapatra, Satyajit
Mohapatra, Nihar Ranjan  
DOI
10.1007/978-981-10-7470-7_6
Volume
711
Abstract
The 64b/66b technique conventionally is suited for low BER fiber optic channels, but can be extended for higher BER channels by including proper error correcting code and preamble. A modified 64b/66b line encoding technique for the design of high speed SERDES is proposed. Unlike earlier 8b/10b technology, run-length is no more guaranteed but is statistically bound. Generated polynomials are statistically tested in MATLAB prior VHDL implementation. Optimal selection of primitive polynomial limits run length to 11 and provides sub-optimal data security. Proposed 64/66b encoding technique reduces overhead by 15.8% (at 6.3% CRC) with respect to conventional 8b/10b, while is also suited for high BER channels like wireless and free space. A performance optimum between security, run-length, ISI and DC equalization, this scheme finds potential application in space camera electronics, 5G technology and other IOT applications like driverless cars that require to handle large volumes of real time data with sufficient security on high BER wireless channels.
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URI
https://d8.irins.org/handle/IITG2025/23025
Subjects
Bit error rate (BER) | Cyclic redundancy check (CRC) | Encoding technique | Inter-Symbol interference (ISI) | Serializer-Deserializer (SERDES)
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